As more functionality is integrated into the PC platform by the inclusion of an increasing number of semiconductor devices, system attributes such as system power consumption, cost, and performance also increase. Performance concerns may be addressed by such methods as coupling devices to the microprocessor directly by placing them on the microprocessor""s Front-Side Bus (FSB). This technique helps to avoid some of the arbitration bottlenecks resulting when several devices are coupled to the microprocessor via a core-logic chipset, such as a Memory Controller Hub (MCH) or xe2x80x9cnorth bridgexe2x80x9d chipset. This method also allows such devices to have a more direct path to system memory resources, thereby reducing the need for costly local memory.
However, cost and power issues may arise due to the added bus logic needed to interface devices to the FSB that are xe2x80x9casymmetricxe2x80x9d in relation to the microprocessor architecture. The term xe2x80x9casymmetricxe2x80x9d refers to non-uniformity of bus-interface architecture and bus protocol between a device, such as a co-processor, and a microprocessor coexisting on the FSB. One approach to this problem is to integrate additional bus logic into the substrate of the co-processor. However, this may result in only marginal improvements in power consumption and system cost, since the amount of bus logic is not significantly reduced.
Therefore, existing methods of interfacing a microprocessor to a co-processing device are not optimal for improving system performance, cost, and power consumption.